Monday, January 30, 2023

Intel has killed off its open-source RISC-V dev environment

Intel appears to have quietly killed off its open source RISC-V developer environment, Pathfinder. 

The news may come as a shock to many SoC architects, software developers, and product research teams, primarily because Pathfinder was only announced in August 2022, however to others, it may have been an expected move.

The company reported a catastrophic end to 2022, with its Q4 alone accounting for $661 million in losses, and has pulled the plug on a number of its other operations. Besides this, 544 of its California-based workers are at risk of redundancy, with the potential for more layoffs globally as the company gears up to what it calls a “meaningful number” of job cuts.

Intel Pathfinder

The 2022 press release unveiling Pathfinder details the number of RISC-V-focused initiatives that have rolled out over the years, indicating Intel’s commitment, however just months later, users began to report that it had been cut.

Intel has since updated its website with a statement that reads:

“We regret to inform you that Intel is discontinuing the Intel Pathfinder for RISC-V program effective immediately.”

The web page directs users to “promptly transition” to alternative RISC-V software tools, highlighting that bug fixes have also been stopped.

The program was designed to help its users develop RISC-V chips using industry-standard toolchains and as such had been supported by a number of RISC-V companies. It was split into a Professional Edition, and a more stripped back Starter Edition for hobbyists looking to give it a go.

Vijay Krishnan remained general manager for RISC-V ventures at the company for over a year and a half until it shut its doors this month, pushing him into a new role as general manager for new initiatives, indicating that Intel is turning its back on its RISC-V operations for now.

TechRadar Pro has asked Intel to confirm its decision to stop the Pathfinder program and whether it plans to continue investing in RISC-V in the future.



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